module sva_ca_implication_3;
    logic clk;
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    logic a, b;
    initial begin
        a=1; b=1; #5;  
        a=0; b=0; #10; 
        a=1; b=0; #10; 
        a=0; b=0; #10; 
        a=1; b=0; #10; 
        a=0; b=0; #10; 
        a=0; b=0; #10;
        $finish;
    end

    // 如果 a 在周期 N 为真, 那么 (b 在周期 N 应为真) 或 (b 在周期 N+1 应为真) 或 (b 在周期 N+2 应为真).
    property p1;
        @(posedge clk) a |-> ##[0:2] b;
    endproperty
    ap1: assert property(p1) $info("ap1 passed"); else $error("ap1 failed");

    initial begin
        $dumpfile("dump.vcd"); $dumpvars;
    end
endmodule

/* Output: QuestaSim
# ** Info: ap1 passed
#    Time: 5 ns Started: 5 ns  Scope: sva_ca_implication_3.ap1 File: sva_ca_implication_3.sv Line: 24
# ** Error: ap1 failed
#    Time: 45 ns Started: 25 ns  Scope: sva_ca_implication_3.ap1 File: sva_ca_implication_3.sv Line: 24
 */